Generally, radio frequency (RF) communication systems include at least two communication units. Each communication unit includes a transceiver for sending and receiving RF signals over one of a plurality of RF channels. Each transceiver includes a frequency synthesizer for generating RF signals.
In frequency synthesis it is desirable to achieve the selected frequency output in as little time as possible with any spurious outputs minimized. The spurious outputs in question are usually associated with a phase detector and occur at the frequency of operation of the phase detector which is equal to the channel spacing in a non-fractional phase locked loop. Thus the phase locked loop bandwidth must be small relative to the channel spacing to minimize the spurious outputs. Reducing the loop bandwidth will increase the time required to achieve the selected frequency.
Fractional N division can overcome this problem by allowing the phase detector to operate at a much higher frequency for the same channel spacing. This allows the phase locked loop bandwidth to be much larger and thus the required lock time is much less. Two examples of fractional division systems can be seen in U.S. Pat. No. 5,093,632 entitled "Latched Accumulator Fractional N Synthesis with Residual Error Correction" authored by Hietala et al and U.S. Pat. No. 5,166,642 entitled "Multiple Accumulator Fractional N Synthesis with Series Recombination" and authored by Hietala. In a limiting case the fractional division scheme can use a very large fractionalization such that the residual spurs will appear as increased sideband noise instead of discrete spurs.
Any fractional division system is not perfect in that there will be residual spurs at the frequency step spacing or excessively increased sideband noise for the limiting case mentioned above. This will occur since the fractional system creates a somewhat randomized sequence to move the main loop divider such that the average frequency is correct. Therefore the fractional sequence contains the desired frequency offset information with an additional residual noise term.
Increasing the number of accumulators and the rate at which the accumulators operate can reduce the amplitude of the residual noise waveform and break up the spurious output at a given offset frequency. Eventually a point will be reached at which the number of accumulators and the rate of their operation cannot be further increased due to speed limitations or limitations of the divider. Thus every system will reach a limit of spurious performance even with a fractional division scheme.
In some systems this spurious limit will not be acceptable. These residual spurs can be further reduced by using a D/A converter to convert some combination of the internal contents of the accumulators into analog form and then apply this analog signal to the loop filter through a coupling capacitor. Such a system is shown for a simple one accumulator case in FIG. 1.
Such a residual error correction system is not well suited for integrated circuit design since the selection of the capacitor will be critical and, even if an accurate capacitor value could be had, the resulting circuit would not maintain the required balance between the divider control port and the residual error correction port over temperature, make tolerance, and aging.
Therefore it would be advantageous to devise a residual error correction method for a fractional N synthesis which can be realized in integrated circuit form and is tolerant to variations in temperature, make tolerance, and aging. Additionally, it would be advantageous for the residual error correction method to improve spurious performance for the number of accumulators and the rate at which they operate.